As is known, differential amplifiers with a fully differential output (fully differential amplifiers) are symmetrical circuit structures with two inputs and two outputs. Two voltages are taken from the outputs, and each voltage is the sum of two components, namely a differential component arising from the difference between input voltages of opposite sign, and a component, called the common-mode component, arising from variations of input voltages having the same sign.
Clearly, the working signal is the differential component which is obtained by taking the voltage between the two output terminals. The common-mode components, however, cause a unilateral voltage to be superimposed on the working signal, this being equivalent to a shift of a reference value of the differential output voltage. In many cases, the central value of the supply voltage of the differential amplifier is selected as this reference voltage, particularly in the case in which the input signals are symmetrical to an input reference voltage. In this way, the maximum dynamic range of the output signal is obtained. In the case of asymmetric input signals, however, it may be convenient to select a different value of the reference voltage.
The common-mode component, when arising from a structural imbalance of the final stage, in other words from components which are not identical in the two branches of the differential circuit, causes an additional shift of the output reference voltage. To prevent these effects of the common-mode component from reducing the output dynamic range, there is a known method of using a feedback control system which is provided by a circuit which senses the output common-mode component and acts on an operating parameter of the differential amplifier in such a way as to make the output reference voltage independent of the common-mode component.
A circuit structure of this type is shown schematically in FIG. 1. A differential amplifier, indicated as a whole by the number 10, comprises two pnp-type bipolar transistors T1 and T2 which are identical to each other and have their emitters connected together, through a first current generator G1, to the positive terminal of the supply voltage, indicated by Vdd. The collectors of the transistors T1 and T2 are connected, each through an active load comprising an npn-type bipolar transistor T3 and T4, to the negative terminal of the supply voltage, represented by the ground symbol. The two transistors T3 and T4 have their bases connected together, through a second current generator G2, to the ground terminal, and their collectors connected to corresponding constant current generators G3 and G4 which are identical to each other. The differential amplifier has two input terminals INP and INM connected to the bases of the input transistors T1 and T2, and two output terminals OUP and OUM connected to the collectors of the said transistors T1 and T2.
A voltage divider consisting of two resistors R of equal resistance is connected between the output terminals OUP and OUM of the differential amplifier 10. The intermediate connection of the divider is connected to the inverting terminal of an operational amplifier 11. A voltage, indicated by V.sub.cm, which is the reference voltage selected for the differential output (for example the central value of the supply voltage of the differential circuit) is applied to the non-inverting terminal of the operational amplifier 11. The voltage divider and the operational amplifier 11 together form a circuit, indicated as a whole by the number 15, for regulating the output reference voltage.
In operation, an error voltage Ve, which is proportional to the deviation of the mean output voltage (V.sub.OUP -V.sub.OUM)/2 from the reference value V.sub.cm, is present at the output of the operational amplifier 11. The error voltage Ve is applied to the differential amplifier 10 to be regulated. In this example, it acts on the generator G1 in such a way as to modify in the same direction and by the same amount the currents in the two branches of the differential amplifier, and thus to modify the output voltages V.sub.OUP and V.sub.OUM with a sign such that the error is cancelled.
However, a solution such as that described above requires a power consumption which in many applications in not negligible, and which leads to the operational amplifier 11 and the resistors R taking up a certain amount of space when the amplifier and the corresponding regulator are formed in an integrated circuit.
Another known solution for the feedback circuit is shown in FIG. 2. Two pairs of differential amplifiers having a common input terminal, to which the common-mode reference voltage V.sub.cm is applied, and having their other two input terminals connected to the outputs V.sub.OUM and V.sub.OUP of the differential amplifier 10, are used to detect the mean value of the output of the differential amplifier to be regulated (not shown). Each amplifier is formed by two identical npn-type bipolar transistors, indicated by T5, T6 and T7, T8, each having its emitter connected to one terminal of the supply voltage, indicated by the ground symbol, through a resistor R1 and a constant current generator G3. The collectors of the transistors T6 and T7 are connected directly to the positive pole of the supply voltage Vdd, and the collectors of the transistors T5 and T8 are connected together at a node N which is connected, through a MOSFET transistor M1 connected as a diode (with the drain and gate terminals in common), to the said positive pole Vdd. The gate terminal of the transistor M1 is connected to one input terminal In1 of an operational amplifier 12. The other terminal In2 of the operational amplifier 12 is connected to the junction between a constant current generator G3, identical to those of the differential amplifiers, whose other terminal is connected to ground, and another MOSFET transistor M2, which is identical to the transistor M1 and is also connected as a diode, with its source terminal connected to the positive pole Vdd. The output of the operational amplifier 12 is connected to the differential amplifier (not shown) which requires the common-mode regulation.
In conditions of perfect balancing, a current I/2, where I is the current generated by each of the generators G3, flows in each branch of the coupled differential amplifiers. The current of two branches is added together at the node N, so that a current I flows through the transistor M1. There will be a voltage determined by the resistance between the source and drain of the transistor M1 at the input In1 of the operational amplifier 12. A current I also flows through the transistor M2, and therefore the same voltage will be present at the terminal In2 of the operational amplifier 12. Consequently, no error voltage will be present at the output of the operational amplifier 12.
As may easily be verified, any imbalance, in other words any variation in the same direction of the voltages V.sub.OUP and V.sub.OUM at the outputs OUP and OUM of the differential amplifier to be regulated, is immediately compensated by the feedback of the circuit described above, and therefore the mean value of the output voltages is maintained at the predetermined reference value V.sub.cm.
The circuit structure described above also has disadvantages, the main disadvantage being a reduced dynamic range; in other words, it operates correctly only with small variations of the output voltages of the differential amplifier to be regulated. Another disadvantage is that the circuit takes up a significant amount of space on an integrated circuit.
A feedback circuit operating with switched capacitors has also been proposed to reduce the power consumption. However, this circuit requires a clock generator at a relatively high frequency, which generates perturbations at the outputs at the clock frequency and at twice this frequency. In some applications, these perturbations are not acceptable.